You might get a "Windows Security" popup about installing a device driver from Jungo, LTD.
Leave the default destination directories of C:\Xilinx.Enable WebTalk to send software, IP and device usage statisitcs to Xilinx.Install WinPCap for Ethernet Hardware Co-Simulation.Sourcery CodeBench Lite for Xilinx Cortex-A9 EABI.Sourcery CodeBench Lite for Xilinx Cortex-A9 GNU/Linux.Select Edition to Install: "ISE Design Suite System Edition + Vivado System Edition" Click "Next".Double click on xsetup.exe (should be the last file in the folder) Browse to the memory stick -> Xilinx_ISE_DS_Win_14.2_P.28xd.3.0.Insert memory disk with installation media.Laptops running on battery power typically take longer to install. It is recommended to plug any laptop into a power outlet while attempting this installation. Xilinx ISE Design Suite 14.2 is used by CSE 20221 Logic Design and Sequential Circuits, CSE 30321 Computer Architecture I, CSE 40522 CPEG Capstone Design, and CSE 60321 Advanced Computer Architecture. GUI=1 : Run the Vivado build in GUI mode instead of batch mode.Program Objectives, Outcomes, and Enrollment.( NOTE: this option is only valid for Xilinx ISE) Requires the project in build-*_* to be built. EXPORT_ONLY=1 : Export build targets from a GUI build to the build directory.PROJECT_ONLY=1 : Only create a Xilinx project for the specified target(s).It is possible to make a target and specific additional options in the form VAR=VALUE in the command. build/usrp_fpga.rpt : System, utilization and timing summary report.build/usrp_fpga_.rpt : System, utilization and timing summary reportĮ310 Targets and Outputs Supported Targets.build/usrp_fpga_.lvbitx : Configuration bitstream for PCIe (NI-RIO).build/usrp_fpga_.bin : Configuration bitstream without header.build/usrp_fpga_.bit : Configuration bitstream with header.1GigE on SFP+ Port0, 10Gig on SFP+ Port1. X3x0 Targets and Outputs Supported Targets build/usrp_fpga.twr : Xilinx timing report.build/usrp_fpga.syr : Xilinx system report.build/usrp_fpga.bin : Configuration bitstream without header.build/usrp_fpga.bit : Configuration bitstream with header.Run make help for more information.ī2x0 Targets and Outputs Supported Targets Navigate to usrp3/top//build directory.source /Xilinx/14.7/ISE_DS/settings32.sh (32-bit platform).source /Xilinx/14.7/ISE_DS/settings64.sh (64-bit platform).To add xtclsh to the PATH and to setup up the Xilinx build environment run.
Please check the Xilinx Requirements document above for the FPGA technology used by your USRP device.